Final Year Project

Simulation of Simple Computer System for Teaching

Project Information

This Final Year Project – Simulation of Simple Computer System for Teaching, is about the development of a graphical simulator of the CPU and memory system, in the hope to enhancing teaching and learning experience in the course COMP2120 Computer Organization. The project aims at delivering two simulation components in one simulator program, one for CPU execution simulation and the other for cache memory simulation.

Student

Wong Yin Lok

Supervisor

Dr. K. P. Chan

Project Objective

The goal of the project, and the purpose of developing such a simulator, is to help students visualize and thus more easily understand the actual operations taking place inside the CPU when programming with instruction sets, and follow closely as well as verify the different cache replacement steps simulated grahpically in real time. On the other hand, teaching staff can utilize the tool to build representations of examples or questions and convey ideas about abstract concepts and tedious executions to students more vividly.

Project Methodology


CPU Execution Simulation

The difficulty of CPU execution simulation in this project lies on the flexibility of instruction customization, that users can define arbitrary instructions with unpredictable effects. The simulator program thus does not have predefined implementation logic to cater for different instructions, instead, a list of 22 elementary hardware-level operations are predefined with expected end-effects that users can utilize to build the instructions from.

The simulator program runs a loop during the simulation, which checks the hardware-level operation currently being executed against the list of 22 supported operations, and implements the simulation logic of that particular operation in action. Therefore it is crucial for users to understand the respective end-effects of the 22 elementary operations in order to understand how to define the instructions to achieve certain functionalities.

The following lists the 22 elementary operations and their corresponding end-effects.

move_via_s1

  1. update value of the data point from the data source
  2. move the data point from the data source to the destination along the S1-Bus
  3. update value of the destination with the value from the data point object

move_via_s2

same as move_via_s1, except S2-Bus is used instead of S1-Bus

move_via_d

same as move_via_s1, except D-Bus is used instead of S1-Bus

inc_pc

  1. update value of the data point from PC
  2. move the data point from PC to IncPC
  3. increment value of data point by four
  4. move the data point from IncPC to PC
  5. update the value of PC from the data point

read_rf_port1

  1. update value of the data point from the register file specified in source operand 1
  2. move the data point from Register File to RFOUT1
  3. update value of RFOUT1 from the data point

read_rf_port2

same as read_rf_port1, except register file specified in source operand 2 is used instead
* note that only the 5th bit in the instruction word is significant in specifying the register file

write_rf

  1. update value of the data point from RFIN
  2. move the data point from RFIN to Register File
  3. update value of the specified register file from the data point

alu_add

  1. update values of the data points from temporary registers A and B respectively
  2. move the data points from A and B to ALU simultaneously
  3. perform addition on the values of the data points
  4. update value of the data point from A with the result after the ALU operation, discard the other data point
  5. move the data point from ALU to temporary register C
  6. update value of C from the data point

alu_sub

same as alu_add, except the ALU operation is substraction, i.e. "A" - "B"

alu_and

same as alu_add, except the ALU operation is bit-wise AND

alu_or

same as alu_add, except the ALU operation is bit-wise OR

alu_not

  1. update values of the data point from temporary register A
  2. move the data point from A to ALU
  3. perform bit-wise NOT on the value of the data point
  4. update value of the data point with the result after the ALU operation
  5. move the data point from ALU to temporary register C
  6. update value of C from the data point

alu_copy

  1. update values of the data point from temporary register A
  2. move the data point from A to ALU
  3. move the data point from ALU to temporary register C
  4. update value of C from the data point

read_instruction

  1. update value of the data point from MAR
  2. move the data point from MAR to External Memory
  3. read memory content with the address data in the data point
  4. update value of the data point with the data from the memory read
  5. move the data point from External Memory to IR
  6. update value of IR from the data point
  7. move the data point from IR to Register File to indicate preparation of the involved register files

read_memory

  1. update value of the data point from MAR
  2. move the data point from MAR to External Memory
  3. read memory content with the address data in the data point
  4. update value of the data point with the data from the memory read
  5. move the data point from External Memory to MBR
  6. update value of MBR from the data point

write_memory

  1. update values of the data points from MAR and MBR respectively
  2. move the data points from MAR and MBR to External Memory
  3. update value of the simulated memory at the corresponding address, i.e. data in MAR, with the specified data, i.e. data in MBR

branch

  1. check for branching condition, if branch, do the following, else continue to the next operations
  2. update value of the data point from MBR
  3. move the data point from MBR to temporary register A
  4. update value of A from the data point
  5. perform an alu_copy
  6. perform a move_via_d from C to PC
  7. skip all remaining operations in the current instruction and continue to the next instruction

dec_sp

  1. update value of the data point from SP
  2. move the data point from SP to +-SP
  3. decrement value of data point by four
  4. move the data point from +-SP to SP
  5. update the value of SP from the data point

inc_sp

same as dec_sp, except increment SP instead of decrement

mar_to_temp

  1. update value of the data point from MAR
  2. move the data point from MAR to TEMP
  3. update the value of TEMP from the data point

temp_to_mar

  1. update value of the data point from TEMP
  2. move the data point from TEMP to MAR
  3. update the value of MAR from the data point

halt

halts the simulation
* note that halt is designed specifically for the simulator to break out of the execution loop, and not seen in real-life CPU

Details on implementing the elementary operations are not included here, but can be found in the Final Report available in the Project Documentation section.


Cache Memory Simulation

Cache Memory Simulation can be enabled optionally with the "Cache Simulation" button in the CPU Simulation window. The simulation runs concurrently with and gets the inputs from CPU Exection Simulation.

There are three places at which cache operations can be triggered. They are the hardware-level action “read_instruction”, “read_memoy” and “write_memory”, which involves accessing the simulated memory. When “read_instruction” or “read_memory” is executed and the data point has graphically reached the External Memory section on the CPU image, the actual read memory protocol of this simulator will take place.

The central idea of simulating cache replacement is to maintain a list of access order for each cache set to serve as the reference from choosing which cache line to be replaced next. In the case when FIFO is chosen, the list acts like a queue. Whenever there is a cache line access, the line is pushed into the tail of the list, if not already in the cache. The cache line at the head of the list will always receive the counter “1”, indicating that it is the next to be replaced. Upon replacement, the cache line at the head of the list is removed and the counter “1” migrates to the new head of the list. For the case of LRU, the mechanism is basically the same, that the head of the list will always receive the counter “1” and be replaced next. The difference lies on updating list upon access or replacement. In LRU, the list no longer serves as a simple queue. When a cache line is accessed in a cache set, the corresponding cache line will be moved to the tail of the list, and the cache line at the head of the list will have its counter updated to “1”.

This section covers only a brief overview to the more important topics of the simulator working mechanism, for details, please go to the relevant parts in the final report.

Project Schedule and Milestones

  • Project Plan 2 Oct 2016

    Phase 1 Inception

  • First Presentation Early Jan 2017

    First Presentation

  • CPU Simulation & Interim Report 22 Jan 2017

    Phase 2 Elaboration

  • Memory Simulation & Final Report 16 Apr 2017

    Phase 3 Construction

  • Final Presentation Mid Apr 2017

    Final Presentation

Project Documentation

All reports and related documentations about this project can be found here.

Project Plan
Interim Report
Final Report
Simulator Executable
User Manual

Latest Update

This project has been completed with the final deliverables uploaded to this site. Potential future works include continuous accessments and patches to catch currently unhandled exceptions. The user manual for the simulator program will be uploaded soon. Possible updates to the simulator program will also be uploaded if any.