Simulation of Simple Computer System for Teaching
This Final Year Project – Simulation of Simple Computer System for Teaching, is about the development of a graphical simulator of the CPU and memory system, in the hope to enhancing teaching and learning experience in the course COMP2120 Computer Organization. The project aims at delivering two simulation components in one simulator program, one for CPU execution simulation and the other for cache memory simulation.
Wong Yin Lok
Dr. K. P. Chan
The goal of the project, and the purpose of developing such a simulator, is to help students visualize and thus more easily understand the actual operations taking place inside the CPU when programming with instruction sets, and follow closely as well as verify the different cache replacement steps simulated grahpically in real time. On the other hand, teaching staff can utilize the tool to build representations of examples or questions and convey ideas about abstract concepts and tedious executions to students more vividly.
The difficulty of CPU execution simulation in this project lies on the flexibility of instruction customization, that
users can define arbitrary instructions with unpredictable effects. The simulator program thus does not have predefined
implementation logic to cater for different instructions, instead, a list of 22 elementary hardware-level operations are
predefined with expected end-effects that users can utilize to build the instructions from.
The simulator program runs a loop during the simulation, which checks the hardware-level operation currently being executed against the list of 22 supported operations, and implements the simulation logic of that particular operation in action. Therefore it is crucial for users to understand the respective end-effects of the 22 elementary operations in order to understand how to define the instructions to achieve certain functionalities.
The following lists the 22 elementary operations and their corresponding end-effects.
halthalts the simulation
Details on implementing the elementary operations are not included here, but can be found in the Final Report available in the Project Documentation section.
Cache Memory Simulation can be enabled optionally with the "Cache Simulation" button in the CPU Simulation window. The
simulation runs concurrently with and gets the inputs from CPU Exection Simulation.
There are three places at which cache operations can be triggered. They are the hardware-level action “read_instruction”, “read_memoy” and “write_memory”, which involves accessing the simulated memory. When “read_instruction” or “read_memory” is executed and the data point has graphically reached the External Memory section on the CPU image, the actual read memory protocol of this simulator will take place.
The central idea of simulating cache replacement is to maintain a list of access order for each cache set to serve as the reference from choosing which cache line to be replaced next. In the case when FIFO is chosen, the list acts like a queue. Whenever there is a cache line access, the line is pushed into the tail of the list, if not already in the cache. The cache line at the head of the list will always receive the counter “1”, indicating that it is the next to be replaced. Upon replacement, the cache line at the head of the list is removed and the counter “1” migrates to the new head of the list. For the case of LRU, the mechanism is basically the same, that the head of the list will always receive the counter “1” and be replaced next. The difference lies on updating list upon access or replacement. In LRU, the list no longer serves as a simple queue. When a cache line is accessed in a cache set, the corresponding cache line will be moved to the tail of the list, and the cache line at the head of the list will have its counter updated to “1”.
This section covers only a brief overview to the more important topics of the simulator working mechanism, for details, please go to the relevant parts in the final report.
This project has been completed with the final deliverables uploaded to this site. Potential future works include continuous accessments and patches to catch currently unhandled exceptions. Possible updates to the simulator program will also be uploaded if any.