January 31 - February 4, 1998

Multithreaded execution is becoming a very important execution model in modern computers, both single and multi-processors. The focus of this workshop is on multithreading execution techniques and systems, including the architecture design and implementation, compilation techniques, system and language support and performance evaluation.

The goal of this workshop is to bring together researchers and practitioners in computer architecture and performance analysis from industry and academia to discuss work-in-progress that utilizes commercial workloads for the evaluation of computer architectures. Also, there will be discussion on the difficulties associated with using commercial workloads to drive new computer architecture designs, including the lack of academic access to database kernel source, and what can be done to overcome these problems. The workshop program will include several invited talks from experts in the field, and a set of talks selected from solicited submissions. The topics covered in the workshop will include characterization of commercial workload behavior, hardware design trade-off analysis using commercial workloads, parallelism and multiprocessing issues, comparison of commercial workload behavior to scientific workload behavior, comparison of end-user workloads to industry standard benchmarks, simulation techniques for predicting the performance of commercial workloads, and application and/or OS kernel algorithm improvements to enhance performance.

The sensitivity of communication mechanisms to bandwidth and latency
Frederic Chong, Rajeev Barua, Fredrik Dahlgren, John Kubiatowicz and Anant Agarwal (University of California at Davis, MIT, and Chalmers University, Sweden)

Credit-Flow-Controlled ATM for MP Interconnection:
the ATLAS I Single-Chip ATM Switch
Manolis Katevenis, Dimitrios Serpanos and Emmanuel Spyridakis (FORTH and University of Crete, Greece)

A Very Efficient Distributed Deadlock Detection Mechanism for Wormhole Networks
P. Lopez, J.M. Martinez and J. Duato (Universidad Politecnica de Valencia, Spain)

Challenging applications on fast networks
Koen Langendoen, Rutger Hofman and Henri Bal (Vrije Universiteit, The Netherlands)

Architectural implications of a family of irregular applications
Dave O'Hallaron, Jonathan Shewchuk, and Thomas Gross (Carnegie Mellon University)

The Architectural Costs of Streaming I/O: A Comparison
of worksations clusters and SMPs
Remzi H. Arpaci-Dusseau, Andrea C. Arpaci-Dusseau, David E. Culler, Joseph M. Hellerstein, and David A. Patterson (University of California Berkeley)

The Effectiveness of SRAM Network caches in Clustered DSM's
Adrian Moga and Michel Dubois (University of Southern California)

Home-based SVM protocols for SMP clusters: Design and Performance,
Rudrajit Samanta, Angelos Bilas, Liviu Iftode, and Jaswinder Pal Singh (Princeton University)

Fine-grain Software Distributed Shared memory on SMP clusters
Daniel Scales, Kourosh Gharachorloo and Anshu Aggarwal (DEC Western Research Laboratory)

PRISM: An Integrated Architecture for Scalable Shared Memory
Kattamuri Ekanadham, Beng-Hong Lim, Pratap Pattnaik, and Marc Snir (IBM T.J. Watson Research Center)

Enhancing Memory Use in Simple Coma: Multiplexed Simple Coma
Sujoy Basu and Josep Torrellas (University of Illinois)

Hardware for Speculative Run-Time Parallelization in Distributed Shared-Memory Multiprocessors
Ye Zhang, Lawrence Rauchwerger, and Josep Torrellas (University of Illinois and Texas A&M University)

Virtual-Physical Registers
Antonio Gonzalez, Jose Gonzalez, and Mateo Valero (University of Catalunya, Spain)

Supporting highly-speculative execution via adaptive branch trees
Tien-Fu Chen (National Chung Cheng University, Taiwan)

Speculative Versioning Cache
Sridhar Gopal, T. N. Vijaykumar, James E. Smith, and Gurindar S. Sohi (University of Wisconsin-Madison)

The Impact of Data Transfer and Buffering Alternatives on Network Interface Design
Shubhendu S. Mukherjee and Mark D. Hill (University of Wisconsin-Madison)

Address Translation Mechanisms In Network Interfaces
Ioannis Schoinas and Mark D. Hill (University of Wisconsin-Madison)

Exploiting Two-Case Delivery for Fast Protected Messaging
Kenneth Mackenzie, John Kubiatowicz, Matthew Frank, Walter Lee, Victor Lee, Anant Agarwal and M. Frans Kaashoek (MIT)

Temporal-based procedure reordering for improved instruction cache performance
John Kalamatianos and David Kaeli (Northeastern University)

Performance evaluation of tiling for the register level
M. Jimenez, J. Llaberia and A. Fernandez (University of Catalunya, Spain)

Treegion Scheduling for Wide Issue Processors
William A. Havanki, Sanjeev Banerjia, and Thomas M. Conte (North Carolina State University)

Communication Across Fault-Containment Firewalls on the SGI Origin
Kaushik Ghosh and Allan Christie (Silicon Graphics)

Efficiently Adapting to Sharing Patterns in Software DSMs
Luis Rodolpho Monnerat and Ricardo Bianchini (University of Rio de Janeiro and Petrobras, Brazil)

Comparative Evaluation of Latency Tolerance Techniques for Software Distributed Shared Memory
Todd C. Mowry, Charles Chan, and Adley Lo (University of Toronto and Carnegie Mellon University)

Using multicast and multithreading to reduce communication in software DSM systems
Evan Speight and John Bennett (Rice University)

FPGA based custom computing machines for irregular problems
David Abramson, Paul Logothetis, Adam Postula and Marcus Randall (Monash University, University of Queensland, and Griffith University, Australia)

Non-Stalling Counter Flow Architecture
Mike Miller, Ken Janik and Shih-Lien Lu (Oregon State University)

Partial sampling with reverse state reconstruction:
A new technique for branch predictor performance estimation
Darren Vengroff and Guang Gao (University of Delaware)